Design pattern correcting method, design pattern forming method, process proximity effect correcting method, semiconductor device and design pattern correcting program

ABSTRACT

A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2004-134011, filed Apr. 28, 2004,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a design pattern correcting method forcorrecting a design pattern, a design pattern forming method for forminga design pattern based on a design rule, a process proximity effectcorrecting method for, when forming a desired pattern planar shape on awafer using a design pattern, implementing a processing for proximityeffect correction, a semiconductor device and a design patterncorrecting program.

2. Description of the Related Art

In recent years, progress of semiconductor manufacturing technology isvery remarkable and semiconductors whose minimum design rule is 0.18 μmhave been mass-produced. Such miniaturization has been achieved byremarkable progresses of such fine pattern forming technology as maskprocess technology, lithography process technology and etching processtechnology.

At a time when the pattern size was sufficiently large, a mask patternhaving the same shape as a pattern written by a designer was formed andthe mask pattern was transferred to resist coated on a wafer with aphotolithography machine, thereby forming the designed mask pattern.However, influence made by refraction of exposure light upon thedimension of the wafer has been increased by the miniaturization of thepattern size, and the process technology for the mask and wafer forforming such a fine pattern accurately has become difficult. Therefore,it has been difficult to form a pattern just the same as a designed oneon a wafer even if the same mask as the design pattern is employed.

In order to improve the correspondence of the design pattern,technologies called optical proximity correction (OPC) for implementinga predetermined correction and process proximity correction (PPC) havebeen used for a mask pattern for forming the same pattern as the designpattern on the wafer.

The OPC technology and PPC technology (hereinafter expressed as PPCincluding OPC) are classified largely to two methods. According to oneof them, a moving amount of an edge constituting a design patterncorresponding to the width of the design pattern or a most proximatedistance between the patterns is specified as a rule, and the edge ismoved following the rule. A second method is to optimize an edge movingamount such that the same pattern as the design pattern can be formed onthe wafer by using a lithography simulator capable of estimating thediffracted light intensity distribution of exposure light. Further, acorrecting method capable of achieving a higher precision correction bycombining these two methods has been proposed (for example, Jpn. Pat.Appln. KOKAI Publication No. 2002-258459).

Generally, the PPC method using the lithography simulator is calledmodel base PPC. According to this method, by comparing an optical imagecalculated from a model with a design pattern, the edge of the patternis moved corresponding to the comparison result. At that time, thedesign pattern needs to be divided to edge groups of a certain unit, andan appropriate correction value is calculated for each edge. Withminiaturization of lithography intensified, the resolution of thepattern on the wafer has been deteriorated more and more, andparticularly, deterioration (meaning that the shape of the patterncannot be formed on the wafer just as the design pattern indicates) ofthe resolution at a corner portion of the pattern is remarkable.

Therefore, when the pattern is divided to edge groups, usually thecorner portion of the pattern in which the deterioration of theresolution is particularly serious is preferentially divided.Consequently, such an edge division that the corner portion of thepattern is optimized is achieved, so that the shape of the cornerportion in which the deterioration of the resolution is serious can beoptimally corrected.

However, examples of the design pattern include a design pattern havinga small step in the vicinity of a corner portion thereof. In the case ofsetting a design rule of the layout or using an automatic layout designtool indispensable for designing a large-scale device, generation of thestep in the vicinity of the pattern corner portion is an unavoidableproblem. Because the edge division is started from the corner portion ofthe pattern as described above, even a minute step is recognized as acorner portion. As a result, predetermined edge division cannot beperformed between an original corner portion and the minute step, andconsequently, the correction is not carried out in a predeterminedmanner at the corner portion in which the deterioration of theresolution is serious, so that a problem may occur in mask formation orthe configuration of the wafer.

In such a pattern having a small step in the vicinity of a cornerportion thereof, conventionally, it is difficult to finish the cornerportion into a desired pattern and this is a main cause whichdeteriorates pattern accuracy.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provideda design pattern correcting method of correcting a design pattern inrelation to a minute step of the design pattern, comprising:

-   -   extracting at least one of two edges extended from a vertex of        the design pattern;    -   measuring a length of the extracted edge;    -   determining whether or not the length of the measured edge is        shorter than a predetermined value;    -   extracting two vertexes connected to the extracted edge if it is        determined that the length of the extracted edge is shorter than        the predetermined value; and    -   reshaping the design pattern to match positions of the two        extracted vertexes with each other.

According to a second aspect of the present invention, there is provideda design pattern correcting method of correcting a design pattern inrelation to a minute step of the design pattern, comprising:

-   -   extracting an edge extended from a vertex of the design pattern;    -   measuring a length of the extracted edge;    -   determining whether or not the length of the measured edge is        shorter than a predetermined value;    -   judging that a design rule is violated to output an error if it        is determined that the length of the edge is shorter than the        predetermined value; and    -   reshaping the design pattern not to violate the design rule.

According to a third aspect of the present invention, there is provideda design pattern process proximity effect correcting method ofcorrecting a design pattern process proximity effect of a design patternin relation to a minute step of the design pattern, comprising:

-   -   extracting an edge extended from a predetermined vertex of the        design pattern;    -   measuring a length of the extracted edge;    -   determining whether or not the length of the measured edge is        shorter than a predetermined value;    -   extracting two vertexes connected to the extracted edge if it is        determined that the length of the extracted edge is shorter than        the predetermined value;    -   dividing the extracted edge into edge units for pattern        correction with a vertex excluding the two extracted vertexes as        a starting point;    -   allocating a correction value for the each divided edge unit;        and    -   resizing the design pattern corresponding to the correction        value for the each allocated edge unit.

According to a fourth aspect of the present invention, there is provideda design pattern process proximity effect correcting method of making aprocess proximity effect correction on a design pattern corrected by thedesign pattern correcting method as recited in the first aspect of thepresent invention.

According to a fifth aspect of the present invention, there is provideda design pattern process proximity effect correcting method of making aprocess proximity effect correction on a design pattern corrected by thedesign pattern correcting method as recited in the second aspect of thepresent invention.

According to a sixth aspect of the present invention, there is provideda mask manufacturing method for manufacturing a mask by using a designpattern corrected by the design pattern process proximity effectcorrecting method as recited in the third aspect of the presentinvention.

According to a seventh aspect of the present invention, there isprovided a mask manufacturing method for manufacturing a mask by using adesign pattern corrected by the design pattern process proximity effectcorrecting method as recited in the fourth aspect of the presentinvention.

According to an eighth aspect of the present invention, there isprovided a mask manufacturing method for manufacturing a mask by using adesign pattern corrected by the design pattern process proximity effectcorrecting method as recited in the fifth aspect of the presentinvention.

According to a ninth aspect of the present invention, there is provideda semiconductor device manufacturing method of manufacturing asemiconductor device, comprising forming a pattern of a desired shape ona wafer by exposing the wafer to light by using a mask manufacturedaccording to the mask manufacturing method as recited in the sixthaspect of the present invention.

According to a tenth aspect of the present invention, there is provideda semiconductor device manufacturing method of manufacturing asemiconductor device, comprising forming a pattern of a desired shape ona wafer by exposing the wafer to light by using a mask manufacturedaccording to the mask manufacturing method as recited in the seventhaspect of the present invention.

According to an eleventh aspect of the present invention, there isprovided a semiconductor device manufacturing method of manufacturing asemiconductor device, comprising forming a pattern of a desired shape ona wafer by exposing the wafer to light by using a mask manufacturedaccording to the mask manufacturing method as recited in the eighthaspect of the present invention.

According to a twelfth aspect of the present invention, there isprovided a program of causing a computer to execute a design patterncorrecting method, comprising:

-   -   extracting at least one of two edges extended from a vertex of        the design pattern;    -   measuring a length of the extracted edge;    -   determining whether or not the length of the measured edge is        shorter than a predetermined value;    -   extracting two vertexes connected to the extracted edge if it is        determined that the length of the extracted edge is shorter than        the predetermined value; and    -   reshaping the design pattern to match positions of the two        extracted vertexes with each other.

According to a thirteenth aspect of the present invention, there isprovided a program of causing a computer to execute a design patterncorrecting method, comprising:

-   -   extracting an edge extended from a vertex of the design pattern;    -   measuring a length of the extracted edge;    -   determining whether or not the length of the measured edge is        shorter than a predetermined value;    -   judging that a design rule is violated to output an error if it        is determined that the length of the edge is shorter than the        predetermined value; and    -   reshaping the design pattern not to violate the design rule.

According to a fourteenth aspect of the present invention, there isprovided a program of causing a computer to execute a design patternprocess proximity effect correcting method, comprising:

-   -   extracting an edge extended from a predetermined vertex of the        design pattern;    -   measuring a length of the extracted edge;    -   determining whether or not the length of the measured edge is        shorter than a predetermined value;    -   extracting two vertexes connected to the extracted edge if it is        determined that the length of the extracted edge is shorter than        the predetermined value;    -   dividing the extracted edge into edge units for pattern        correction with a vertex excluding the two extracted vertexes as        a starting point;    -   allocating a correction value for the each divided edge unit;        and    -   resizing the design pattern corresponding to the correction        value for the each allocated edge unit.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a diagram showing a finished pattern shape on a wafer to adesign pattern 11 when there is no minute step in the vicinity of apattern corner portion;

FIG. 2 is a diagram showing a pattern shape of a pattern after OPC ofthe design pattern in FIG. 1;

FIG. 3 is a diagram showing a finished pattern shape on the wafer afterOPC of the design pattern of FIG. 1;

FIG. 4 is a diagram showing a finished pattern shape on the wafer to thedesign pattern 11 when there is a minute step in the vicinity of thepattern corner portion;

FIG. 5 is a diagram showing a pattern shape after OPC of the designpattern in FIG. 4;

FIG. 6 is a diagram showing a finished pattern shape on the wafer afterOPC of the design pattern of FIG. 5;

FIG. 7 shows an example of a flow chart for correcting a design patternin which a minute step exists in the vicinity of the pattern cornerportion;

FIG. 8 shows an example of a flow chart for correcting a design patternin which a minute step exists in the vicinity of the pattern cornerportion;

FIG. 9 shows an example of a flow chart for correcting a design patternin which a minute step exists in the vicinity of the pattern cornerportion;

FIG. 10 is a diagram showing a design pattern in which a minute stepexists in the vicinity of the pattern corner portion before correction;

FIG. 11 is a diagram showing the design pattern shown in FIG. 10 aftercorrection;

FIG. 12 shows a flow chart for correcting the design pattern shown inFIG. 10;

FIG. 13 is a diagram showing a design pattern in which a minute stepexists in the vicinity of the pattern corner portion before correction;

FIG. 14 is a diagram showing the design pattern shown in FIG. 13 aftercorrection;

FIG. 15 shows a flow chart for correcting the design pattern shown inFIG. 13;

FIG. 16 is a diagram showing a design pattern in which a minute stepexists in the vicinity of the pattern corner portion before correction;

FIG. 17 is a diagram showing the design pattern shown in FIG. 16 aftercorrection;

FIG. 18 shows a flow chart for correcting the design pattern shown inFIG. 16;

FIG. 19 is a diagram showing a design pattern in which a minute stepexists in the vicinity of the pattern corner portion before correction;

FIG. 20 is a diagram showing the design pattern shown in FIG. 19 aftercorrection;

FIG. 21 shows a flow chart for correcting the design pattern shown inFIG. 19;

FIG. 22 is a diagram showing a design pattern in which two minute stepsexist in the vicinity of the pattern corner portion before correction;

FIG. 23 is a diagram showing the design pattern shown in FIG. 22 aftercorrection of the single minute step;

FIG. 24 is a diagram showing the design pattern shown in FIG. 22 aftercorrection of the two minute step;

FIG. 25 is a cross sectional view showing a device structure in a stepof a method of manufacturing a semiconductor device according to anotherembodiment of the present invention, which is used to explain themanufacturing method;

FIG. 26 is a cross sectional view showing a device structure in a stepfollowing to the step in FIG. 25 of the method of manufacturing thesemiconductor device according to the embodiment of the presentinvention, which is used to explain the manufacturing method of thesemiconductor device;

FIG. 27 is a cross sectional view showing a device structure in a stepfollowing to the step in FIG. 26 of the method of manufacturing thesemiconductor device according to the embodiment of the presentinvention, which is used to explain the manufacturing method of thesemiconductor device;

FIG. 28 is a cross sectional view showing a device structure in a stepfollowing to the step in FIG. 27 of the method of manufacturing thesemiconductor device according to the embodiment of the presentinvention, which is used to explain the manufacturing method of thesemiconductor device;

FIG. 29 is a cross sectional view showing a device structure in a stepfollowing to the step in FIG. 28 of the method of manufacturing thesemiconductor device according to the embodiment of the presentinvention, which is used to explain the manufacturing method of thesemiconductor device;

FIG. 30 is a cross sectional view showing a device structure in a stepfollowing to the step in FIG. 29 of the method of manufacturing thesemiconductor device according to the embodiment of the presentinvention, which is used to explain the manufacturing method of thesemiconductor device; and

FIG. 31 is a cross sectional view showing a device structure in a stepfollowing to the step in FIG. 30 of the method of manufacturing thesemiconductor device according to the embodiment of the presentinvention, which is used to explain the manufacturing method of thesemiconductor device.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described with reference tothe accompanying drawings.

First Embodiment

FIGS. 1 to 3 show changes of a pattern in case where a minute stepexists in the vicinity of a pattern corner portion. FIGS. 4 to 6 showchanges of a pattern in case where no minute step exists in the vicinityof the pattern corner portion.

FIGS. 1 to 3 show examples in which no minute step exist in the vicinityof the pattern corner portion, FIG. 1 shows a finished pattern shape 12on a wafer to a design pattern 11, FIG. 2 shows a mask pattern shape 13after OPC and FIG. 3 shows a finished pattern shape 14 on the waferafter OPC. FIGS. 4 to 6 show examples in which a minute step exists inthe vicinity of the pattern corner portion and FIG. 4 shows the finishedpattern shape 12 on the wafer to the design pattern 11, FIG. 5 shows amask pattern shape 13 after OPC and FIG. 6 shows a finished patternshape 14 on the wafer after OPC.

Because if no minute step exists as shown in FIGS. 1 to 3, edge divisioncan be implemented to a predetermined position with the corner portionas a starting point, the finished planar shape of the corner portion onthe wafer can be finished as desired.

To the contrary, if a minute step exists in the vicinity of the cornerportion, as shown in FIGS. 4 to 6, the minute step is regarded identicalto the corner portion under a conventional method. Therefore, the edgecannot be divided at a predetermined position due to the existence ofthe minute step. As a result, no predetermined shape can be obtained onthe wafer, thereby reducing yield rate of the device and maskproduction.

Then, according to this embodiment, a design rule is formed so as toexclude such a minute step at the design stage as described below. Thatis, explaining with reference to a flow chart shown in FIG. 7,

-   1. Extracting a corner portion (vertex) of a design pattern (step    S11)-   2. Extracting an edge extended from the extracted corner portion    (step S12)-   3. Measuring the length of the extracted edge (step S13)-   4. Determining the length of the measured edge (step S14)-   5. If it is determined that the length of the measured edge is    shorter than a predetermined value (when it is determined that it is    a minute step), that is, if the determination result is YES, it is    recognized that the design rule is violated (step S14) and error is    outputted. Here, the predetermined value mentioned here is less than    a minimum value which limits the design pattern.

Then, by reshaping the pattern of a portion which is determined to be anerror, the minute step of the design pattern is excluded (step S15).Next, whether or not all corner portions are extracted is determined(step S16) and if the result is YES, this procedure is finished. If thedetermination result is NO, the procedure returns to step S11 forextracting the corner portion of the design pattern. If thedetermination result is NO in step S14 for determining the length of theextracted edge, whether or not all the corner portions are extracted isdetermined (step S17) and if the determination result is YES, thisprocedure is finished. If the determination result is NO, the procedurereturns to step S11 for extracting the corner portion of the designpattern.

In the above-described steps, the design pattern is corrected. Then,process proximity effect correction is carried out on the design patterncorrected in such a way and a mask is manufactured with the designpattern which has undergone the process proximity effect correction.

Second Embodiment

Next, a second embodiment of the invention in which edge division iscarried out without affecting the edge division even if a minute stepexists in a design pattern will be described with reference to a flowchart of FIG. 8.

-   1-4. Step S21 to step S24 which are the same as step S11 to step S14    of the first embodiment are carried out.-   5. If it is determined that the length of the edge is shorter than a    predetermined value in step S24 (when it is determined to be a    minute step), that is, the determination result is YES, the    extracted corner portion (vertex constituting the minute step) is    not adopted as an edge division start point (step S25).-   6. If the determination result is NO in step S24, the extracted    corner portion is adopted as an edge division start point (step    S27).-   7. A correction value is allocated for each division unit of the    edge and resize is made corresponding to the correction value (step    S28).

Next, whether or not all corner portions are extracted is determined(step S29) and if the result is YES, this procedure is finished. If thedetermination result is NO, the procedure returns to step S21 forextracting the corner portion of the design pattern. If thedetermination result is YES in step S24 for determining the length ofthe extracted edge and the extracted corner portion is not adopted as anedge division start point (step S25), whether or not all the cornerportions are extracted is determined (step S26) and if the determinationresult is YES, this procedure is finished. If the determination resultis NO, the procedure returns to step S21 for extracting the cornerportion of the design pattern.

In the above-described steps, the process proximity effect correction iscarried out to the design pattern. Then, a mask is manufactured with thedesign pattern which has undergone process proximity effect correction.

Third Embodiment

Next, a method for forming a new design pattern by excluding a minutestep existing in a design pattern will be described with reference to aflow chart of FIG. 9. According to this method, following steps areexecuted.

-   1. Extracting a corner portion of a design pattern (step S31)-   2. Extracting an edge extended from the extracted corner portion    (step S32)-   3. Measuring the length of the extracted edge (step S33)-   4. Determining the length of the extracted edge (step S34)-   5. If it is determined that the length of the edge is short (when    determined to be a minute step), coordinates of two vertexes    constituting those edges are extracted (step S35).-   6. The design pattern is reshaped such that the coordinates of the    extracted two vertexes coincide each other (step S36).

Next, whether or not all corner portions are extracted is determined(step S37) and if the result is YES, this procedure is finished. If thedetermination result is NO, the procedure returns to step S31 forextracting the corner portion of the design pattern. If thedetermination result is NO in step S34 for determining the length of theextracted edge, whether or not all the corner portions are extracted isdetermined (step S38) and if the determination result is YES, thisprocedure is finished. If the determination result is NO, the procedurereturns to step S31 for extracting the corner portion of the designpattern.

In the above-described steps, a design pattern excluding the minute stepis formed. Then, the process proximity effect correction is carried outto the formed design pattern and a mask is manufactured using the designpattern which has undergone the process proximity effect correction.

FIG. 10 shows a design pattern formed according to a conventionalmethod, namely, a design pattern before the correction of thisembodiment is carried out, and FIG. 11 shows an example of the designpattern formed by correction according to this embodiment. FIG. 12 showsthe above-mentioned corrected flow chart.

As for the design pattern of FIG. 10, a corner portion Q of a pattern 31is extracted (step 41), and two edges QP and QR extended from the cornerportion Q are extracted (step 42). The lengths of the two extractededges QP and QR are measured (step 43). If the lengths of both the QPand QR are a predetermined value or less, it is determined that thisportion is a minute step (step 44). Two vertex coordinates P and Qconstituting the edge QP are extracted (step 45), and the design patternis reshaped such that these coordinates coincide each other (step 46).Likewise, two vertex coordinates Q and R which constitute the edge QRare extracted (step 47), and the design pattern is reshaped such thatthese coordinates coincide each other (step 48). The vertex P coincidingwith the vertex Q and the vertex R coinciding with the vertex Q meansthe vertex P coinciding with the vertex R. Therefore, by extending aline other than QP including the vertex P while extending a line otherthan QR including the vertex R, the two vertexes P, R are matched with avertex S as shown in FIG. 11. A hatched area 32 in FIG. 11 obtained inthis way is a pattern added portion. That is, according to thisembodiment, a pattern having no step can be formed by adding the hatchedarea 32 as shown in FIG. 11.

FIG. 13 shows a design pattern to be formed according to theconventional method, namely, a design pattern before the correctionbased on this embodiment. FIG. 14 shows an example of the design patternto be formed by correction according to this embodiment. FIG. 15 shows aflow chart of the correction.

As for the design pattern of FIG. 13, a corner portion Q of a pattern 41is extracted (step 51), and two edges QP and QR extended from the cornerportion Q are extracted (step 52). The lengths of the two extractededges QP and QR are measured (step 53). If the lengths of both the QPand QR are a predetermined value or less, it is determined that thisportion is a minute step (step 54). Two vertex coordinates P and Qconstituting the edge QP are extracted (step 55), and the design patternis reshaped such that these coordinates coincide each other (step 56).Likewise, two vertex coordinates Q and R which constitute the edge QRare extracted (step 57), and the design pattern is reshaped such thatthese coordinates coincide each other (step 58). The vertex P coincidingwith the vertex Q and the vertex R coinciding with the vertex Q meansthe vertex P coinciding with the vertex R. Therefore, by extending aline other than QP including the vertex P while extending a line otherthan QR including the vertex R, the two vertexes P, R are matched with avertex S as shown in FIG. 14. A deleted area 43 in FIG. 14 obtained inthis way is a pattern deleted portion. That is, according to thisembodiment, a pattern having no step can be formed, by deleting theblank area 43 as shown in FIG. 14.

FIG. 16 shows a design pattern formed according to the conventionalmethod, namely, a design pattern before correction based on thisembodiment. FIG. 17 shows an example of the design pattern formed bycorrection according to this embodiment. FIG. 18 shows a flow chart ofthe correction.

As for the design pattern of FIG. 16, a corner portion Q of a pattern 51is extracted (step 61), and two edges QP and QR extended from the cornerportion Q are extracted (step 62). The lengths of the two extractededges QP and QR are measured (step 63). If the lengths of both the QPand QR are a predetermined value or less, it is determined that thisportion is a minute step (step 64). Two vertex coordinates P, Qconstituting the edge QP are extracted (step 65), and the design patternis reshaped such that these coordinates coincide each other (step 66).Likewise, two vertex coordinates Q, R which constitute the edge QR areextracted (step 67), and the design pattern is reshaped such that thesecoordinates coincide each other (step 68). The vertex P coinciding withthe vertex Q and the vertex R coinciding with the vertex Q means thevertex P coinciding with the vertex R. Therefore, by extending a lineother than QP including the vertex P while extending a line other thanQR including the vertex R, the two vertexes P, R are matched with avertex S as shown in FIG. 17. A blank area 53 in FIG. 17 obtained inthis way is a pattern deleted portion. That is, according to thisembodiment, a pattern having no step can be formed, by deleting theblank area 53 as shown in FIG. 17.

FIG. 19 shows a design pattern formed according to the conventionalmethod, namely, a design pattern before correction based on thisembodiment. FIG. 20 shows an example of the design pattern formed bycorrection according to this embodiment. FIG. 21 shows a flow chart ofthe correction.

As for the design pattern of FIG. 19, corner portions P and Q of apattern 61 is extracted (step 71), and an edge PQ extended from thecorner portions P and Q is extracted (step 72). The length of theextracted edge PQ is measured (step 73). If the length of the PQ is apredetermined value or less, it is determined that this portion is aminute step (step 74). Two vertex coordinates P and Q constituting theedge PQ are extracted (step 75), and the design pattern is reshaped suchthat these coordinates coincide each other (step 76). That is, byextending a line including the vertex P while extending a line includingthe vertex Q, the two vertexes P, Q are matched with a vertex S as shownin FIG. 20. A hatched area 62 in FIG. 20 obtained in this way is apattern added portion. According to this embodiment, a pattern having nostep can be formed by adding the hatched area 62 as shown in FIG. 20.

According to the embodiments, by detecting the length of an edge formingthe corner portion to a design pattern possessing the minute step, theminute step can be extracted. By correcting the design pattern based onthe extracted minute step, deterioration of correction accuracy at thecorner portion can be prevented, thereby making it possible to form ahighly accurate pattern.

If a plurality minute steps are disposed continuously as shown in FIG.22, the minute steps having an edge length less than a predeterminedvalue can be deleted by executing the processing described above pluraltimes. FIG. 22 shows an original design pattern and FIG. 23 shows adesign pattern after the processing indicated by the above embodimentsis executed a single time. By applying the above-described processing tothe design pattern shown in FIG. 23 again, the minute steps can bedeleted. FIG. 24 shows the design pattern after the second processing iscarried out. By executing the processing indicated by the embodimentsplural times, the minute pattern formed with edges less than thepredetermined value can be deleted from the design pattern, so that ahighly accurate pattern in which deterioration of the correctionaccuracy at the corner portion can be formed.

Fourth Embodiment

Next, a method of manufacturing a semiconductor device according to afourth embodiment of the present invention will be explained withreference to FIGS. 25-31.

Here, a method of manufacturing a MOS (Metal Oxide Semiconductor)transistor as an example of semiconductor devices, by using a photo maskprovided by the above-described embodiments, will be explained.

As shown in FIG. 25, a gate insulating film 72 is formed on a siliconsemiconductor substrate 71 by using a thermal oxidation method, apolysilicon film 73 is formed on the gate insulating film 72 by CVD(Chemicla Vapor Deposition) method. After that, the polysilicon film 73and the gate insulating film 72 are subjected to patterning to form agate structure comprised of the polysilicon film 73 and the gateinsulating film 72. To form this gate structure, a photo resist layer 74is formed on the polysilicon film 73, and then the photo resist layer 74is patterning-processed by lithography to form a photo resist pattern.

At this patterning of the photo resist layer 74, use is made of a mask75 manufactured by using a design pattern corrected by the designpattern process proximity effect correcting method as described in thesecond embodiment. To be specific, the mask 75 is mounted above thesilicon semiconductor substrate 71, and light beams are radiated ontothe silicon semiconductor substrate 71 via the mask 75 from a light beamsource, not shown, to transfer a pattern of the mask 75 to the photoresist layer 74.

Subsequently, the transferred pattern is developed so that a photoresist pattern 74 corresponding to the pattern of the mask 75 is formed,as shown in FIG. 26.

Next, as shown in FIG. 27, the polysilicon film 73 and the gateinsulating film 72 are patterning-processed to form the gate structurecomprised of the polysilicon film 73 and the gate insulating film 72, byusing the photo resist pattern 74 as an etching mask. Then, impuritiesare implanted into the silicon semiconductor substrate 71 to formsource/drain regions 76, by using the photo resist pattern 74, thepolysilicon film 73 (polysilicon electrode) and the gate insulating film72, as a mask.

Subsequently, the photo resist pattern 74 is removed by a known method.Then, as shown in FIG. 28, an interlayer insulating film 77 is formedover the silicon semiconductor substrate 71 by CVD method. Followingthis, openings are formed in the interlayer insulating film 77 forcontact to the polysilicon electrode 73 and source/drain regions 76. Toform the openings, a photo resist layer 78 is formed on the interlayerinsulating film 77, and then the photo resist layer 78 ispatterning-processed by lithography to form a photo resist pattern.

At this patterning of the photo resist layer 78, use is made of a mask79 manufactured by using a design pattern corrected by the designpattern process proximity effect correcting method as described in thesecond embodiment. To be specific, the mask 79 is mounted above thesilicon semiconductor substrate 71, and light beams are radiated ontothe silicon semiconductor substrate 71 via the mask 79 from a light beamsource, not shown, to transfer a pattern of the mask 79 to the photoresist layer 78.

Subsequently, the transferred pattern is developed so that a photoresist pattern 78 corresponding to the pattern of the mask 79 is formed,as shown in FIG. 29.

Next, as shown in FIG. 30, the interlayer insulating film 77 ispatterning-processed to form the openings for contact to the polysiliconelectrode 73 and source/drain regions 76, by using the photo resistpattern 78 as an etching mask.

Subsequently, the photo resist pattern 78 is removed by a known method.Then, as shown in FIG. 31, contact metals 80 are formed in the openingsfor contact to the polysilicon electrode 73 and source/drain regions 76,and wiring metals 81 contacting the contact metals 50 are formed on theinterlayer insulating film 77 by a known method. With the manufacturingmethod, since use is made in each of the patterning processes of a maskmanufactured by using a design pattern corrected by the design patternprocess proximity effect correcting method as described in the abovedescribed embodiments (for example, the second example), desiredpatterns are formed on the semiconductor wafer with high accuracy,resulting in providing a highly accurate semiconductor device.

According to the embodiments of the present invention, it is possible toimprove dimensional precision of a resist pattern formed in an exposuretechnique which forms a liquid film in a local region on a resist film.

According to the embodiments of the present invention, the shape of thecorner portion in which deterioration of the resolution remarkablyappears can be finished as a desired pattern indicates. As a result, theyield of device manufacturing can be greatly improved.

The minute steps disposed in the vicinity of the corner portion of thedesign pattern is an obstacle to forming a desired shape on the waferfor the process proximity effect correction, thereby inducingdeterioration of the yield of the device. According to the embodimentsof the present invention, by forming a pattern excluding the minutesteps and carrying out the process proximity effect correction on thedata, the planar shape on the wafer at the pattern corner portion can befinished into a desired pattern.

In the meantime, the present invention is not restricted to theabove-described respective embodiments but may be modified in variousways within a scope not departing from the gist of the invention. Therehave been described the design pattern forming method based on the newdesign rule as the first embodiment, the process proximity effectcorrecting method as the second embodiment, the design patterncorrecting method for correcting the design pattern as the thirdembodiment, and the method of manufacturing a semiconductor device asthe fourth embodiment. The present invention can be applied to the maskpattern forming method for forming a pattern subjected to the processproximity effect correction for the design pattern formed by the firstand third embodiments. Further, the present invention can be applied tothe mask manufacturing method for manufacturing a mask from the maskpattern formed according to the first to third embodiments.

In addition, the design pattern correcting method and the design patternprocess proximity effect correcting method described in the embodimentscan be distributed by storing as a program which can be executed by acomputer in a recording medium such as a magnetic disk (such as floppy(registered trademark) disk or hard disk), an optical disk (such as aCD-ROM or DVD), an optical magnetic disk (such as MO), or asemiconductor memory. Any types of recording mediums can be used as longas the program can be recorded in the recording mediums and executed bya computer. The program including a sequence of procedures can bedistributed as recording mediums via a communication network such as LANor Internet. Any types of computers can be used as long as the computerscan execute the above-described processing operations by reading theprogram recorded in a recording medium and controlling an operation inaccordance with the program.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A design pattern correcting method of correcting a design pattern inrelation to a minute step of the design pattern, comprising: extractingat least one of two edges extended from a vertex of the design pattern;measuring a length of the extracted edge; determining whether or not thelength of the measured edge is shorter than a predetermined value;extracting two vertexes connected to the extracted edge if it isdetermined that the length of the extracted edge is shorter than thepredetermined value; and reshaping the design pattern to match positionsof the two extracted vertexes with each other.
 2. A design patterncorrecting method of correcting a design pattern according to claim 1,wherein a point at which edges other than the extracted edge areextended and intersected is regarded as a new vertex to match thepositions of the two vertexes with each other.
 3. A design patterncorrecting method of correcting a design pattern according to claim 1,wherein, when it is determined that the lengths of the two edges areshorter than the predetermined value, the design pattern is reshaped tomatch the positions of two vertexes other than a common vertex of theedges with each other.
 4. A design pattern correcting method ofcorrecting a design pattern according to claim 3, wherein a point atwhich edges other than the extracted edge are extended and intersectedis regarded as a new vertex to match the positions of the two vertexeswith each other.
 5. A design pattern correcting method of correcting adesign pattern according to claim 1, wherein the predetermined value isless than a minimum width which limits the design pattern.
 6. A designpattern correcting method of correcting a design pattern in relation toa minute step of the design pattern, comprising: extracting an edgeextended from a vertex of the design pattern; measuring a length of theextracted edge; determining whether or not the length of the measurededge is shorter than a predetermined value; judging that a design ruleis violated to output an error if it is determined that the length ofthe edge is shorter than the predetermined value; and reshaping thedesign pattern not to violate the design rule.
 7. A design patterncorrecting method of correcting a design pattern according to claim 6,wherein the predetermined value is less than a minimum width whichlimits the design pattern.
 8. A design pattern process proximity effectcorrecting method of correcting a design pattern process proximityeffect of a design pattern in relation to a minute step of the designpattern, comprising: extracting an edge extended from a predeterminedvertex of the design pattern; measuring a length of the extracted edge;determining whether or not the length of the measured edge is shorterthan a predetermined value; extracting two vertexes connected to theextracted edge if it is determined that the length of the extracted edgeis shorter than the predetermined value; dividing the extracted edgeinto edge units for pattern correction with a vertex excluding the twoextracted vertexes as a starting point; allocating a correction valuefor said each divided edge unit; and resizing the design patterncorresponding to the correction value for said each allocated edge unit.9. A design pattern process proximity effect correcting method,according to claim 8, wherein the predetermined value is less than aminimum width which limits the design pattern.
 10. A design patternprocess proximity effect correcting method of making a process proximityeffect correction on a design pattern corrected by the design patterncorrecting method as recited in claim
 1. 11. A design pattern processproximity effect correcting method of making a process proximity effectcorrection on a design pattern corrected by the design patterncorrecting method as recited in claim
 6. 12. A mask manufacturing methodfor manufacturing a mask by using a design pattern corrected by thedesign pattern process proximity effect correcting method as recited inclaim
 8. 13. A mask manufacturing method for manufacturing a mask byusing a design pattern corrected by the design pattern process proximityeffect correcting method as recited in claim
 10. 14. A maskmanufacturing method for manufacturing a mask by using a design patterncorrected by the design pattern process proximity effect correctingmethod as recited in claim
 11. 15. A semiconductor device manufacturingmethod of manufacturing a semiconductor device, comprising forming apattern of a desired shape on a wafer by exposing the wafer to light byusing a mask manufactured according to the mask manufacturing method asrecited in claim
 12. 16. A semiconductor device manufacturing method ofmanufacturing a semiconductor device, comprising forming a pattern of adesired shape on a wafer by exposing the wafer to light by using a maskmanufactured according to the mask manufacturing method as recited inclaim
 13. 17. A semiconductor device manufacturing method ofmanufacturing a semiconductor device, comprising forming a pattern of adesired shape on a wafer by exposing the wafer to light by using a maskmanufactured according to the mask manufacturing method as recited inclaim
 14. 18. A program of causing a computer to execute a designpattern correcting method, comprising: extracting at least one of twoedges extended from a vertex of the design pattern; measuring a lengthof the extracted edge; determining whether or not the length of themeasured edge is shorter than a predetermined value; extracting twovertexes connected to the extracted edge if it is determined that thelength of the extracted edge is shorter than the predetermined value;and reshaping the design pattern to match positions of the two extractedvertexes with each other.
 19. A program of causing a computer to executea design pattern correcting method, comprising: extracting an edgeextended from a vertex of the design pattern; measuring a length of theextracted edge; determining whether or not the length of the measurededge is shorter than a predetermined value; judging that a design ruleis violated to output an error if it is determined that the length ofthe edge is shorter than the predetermined value; and reshaping thedesign pattern not to violate the design rule.
 20. A program of causinga computer to execute a design pattern process proximity effectcorrecting method, comprising: extracting an edge extended from apredetermined vertex of the design pattern; measuring a length of theextracted edge; determining whether or not the length of the measurededge is shorter than a predetermined value; extracting two vertexesconnected to the extracted edge if it is determined that the length ofthe extracted edge is shorter than the predetermined value; dividing theextracted edge into edge units for pattern correction with a vertexexcluding the two extracted vertexes as a starting point; allocating acorrection value for said each divided edge unit; and resizing thedesign pattern corresponding to the correction value for said eachallocated edge unit.